Logic Encryption for Resource Constrained Designs

Logic Encryption is a hardware security technique that protects integrated circuit designs are fabricated at untrusted pure play foundries from being pirated or maliciously modified. In the technique, logic gates added to design driven by an key input bus, such correct behavior of recovered with only exact pattern. However, power, performance, and area (PPA) cost implementing encryption has often been ignored in literature favor increasing level provided. This proved be significant hurdle transitioning method use commercial-grade systematic methodology constraining needed. this paper, we propose generalized Constraint-Directed (CDLE) methodology. CDLE, potential space encrypted versions searched apply under PPA constraints. Two example CDLE methods proposed. The first concurrent tree search which uses commercial tools sample for their determine optimal strategy. method, accurately analyzed heavy runtime. second machine learning approach estimates predict model developed work limited, but results promising as direction study encryption. Detailed experimental evaluating both presented.